Stacked MOS transistor
US4476475A · kind A · utility
38Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1982 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Nov 19, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.