CMOS Input and output protection circuit
US4476476A · kind A · utility
25Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1981 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Apr 1, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
Abstract
A CMOS gate protection diode clamping the input terminal to substrate potential is prevented from injecting carriers into the substrate and causing SCR latchup by forming the diode as a well to substrate junction, surrounded by another, reverse-biased, well, to both reduce injection and collect parasitic injected carriers before they can diffuse to cause latchup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.