Horizontal scanning frequency multiplying circuit
US4476490A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1982 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Mar 17, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with a horizontal synchronizing signal having a horizontal scanning frequency f.sub.H, which is set by this horizontal synchronizing signal, a phase-locked-loop, and a counter. The phase-locked-loop comprises a voltage controlled oscillator for producing a signal having a frequency Nf.sub.H (N is an integer over 1) which is N times the horizontal scanning frequency f.sub.H, a frequency divider for frequency-dividing an output signal frequency of the voltage controlled oscillator, and a phase comparator supplied with one output signal of the flip-flop and an output signal of the frequency divider, for comparing phases of these signals and applying an output error signal to the voltage controlled oscillator to control the oscillation frequency of the voltage controlled oscillator. The counter is supplied with the other output signal of said flip-flop which is reset by this output signal, and supplied with the output signal of the voltage controlled oscillator within the phase-locked-loop as a clock signal, and produces a counted output every time the clock signal is counted for a predetermined counting…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.