Page storage control methods and means
US4476524A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1981 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Jul 2, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiment provides an independent data bus path between a random access page storage (PS), and a main storage (MS), wherein this independent data bus does not pass through any channel processor (CH) or central processor (CP). Page data transfers on the independent data bus can be controlled either (1) asynchronously by a channel processor (independently of any central processor instruction stream), or (2) synchronously by a CP (independently of any CH operation). Novel CP instructions enable the CP to synchronously control the transfer of pages in either direction on the independent data bus. A channel program for controlling the page transfer may be initiated by a start I/O (SIO) or start subchannel (SSCH) instruction in the CPU, and it accesses a special field in a channel address word (CAW) that designates the use of the page storage. Novel PS channel command words (CCWs) in the channel program enable CH to control page transfers on the independent data bus. A channel program may intermix both I/O CCWs and page storage CCWs to obtain a page transfer between an I/O device and PS through MS, which obtains three-media control by a single channel program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.