Programmable address buffer for partial products
US4476546A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 1982 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Mar 19, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable address buffer for coupling external addresses to a desired pair of internal memory addresses includes A and B address inputs 11 and 12, a B address output 15 coupled to the B address input 12, a first inverter I30 coupled to the B address input and a B address output, a first switch S2 coupled to switchably connect one of the A and B address inputs 11 and 12 to a node, an A address output coupled to the first node, a second inverter I10 connected to the first node, a third inverter I20 connected between the second node and an A output 14, and a second switch S1 coupled to the second node to switchably connect one of the first node or the second inverter I10 to the second node. In another embodiment an electrical circuit for controlling the addressing of functional sections of a partially functional product includes a first pin 100 coupled by a first fuse F.sub.1 to a first address buffer 150, and a second pin 110 coupled by a second fuse F.sub.5 to a second address buffer 160, a fusible connection F.sub.4 between the second pin 110 and the first buffer 150, and fusible connections F.sub.2, F.sub.3, F.sub.6, and F.sub.7 to each address buffer to connect that address …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.