Method of error correction
US4476562A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1983 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Sep 28, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Error detection and correction method and apparatus for use with digital data signals, which have been coded using cross-interleaving error correction codes with added check words prior to transmission, employ a plurality (k) of syndrome word signals S.sub.O. . . S.sub.k-1) that are generated by multiplying one block (V.sup.t) of the received digital data signals with a parity check matrix, in which each element of one predetermined row is a function of a root of an irreducible polynomial on Galois field GF (2), the syndromes are used to obtain a set of constant word signals (A, B, and C). Error detection and correction is based on these developed syndrome word and constant word signals, in which if selected syndrome word and constant word signal levels are equal to zero, there is no error word declared; if selected ones of the syndrome word and constant word signal levels are equal to zero and selected other signal levels are not equal to zero, then one error word is declared and error correction is performed by calculation of the syndrome word signals which have been determined to be the equivalent of error pattern signals; and if selected constant word signal levels are not equa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.