Fast MOS driver stage for digital signals

US4477735A · kind A · utility

Assignee

• ITT Industries · US

Inventors

• Wolfgang Gollinger · Gundelfingen, DE
• Daniel Mlynek · Heimbach, DE

Key dates

• Filing date: Dec 14, 1981
• Grant date: Oct 16, 1984
• Expiry date: Dec 14, 2001

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/023
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A fast MOS driver circuit for digital signals having a small current consumption and a good signal-to-noise ratio comprises an output inverter, a pre-inverter and of an enhancement-type transistor having its source-drain path connected in parallel to that of the load transistor of the output inverter (IA). The gate of the enhancement-type transistor and the gates of the load transistors of the output and pre-inverters are coupled to the output of the pre-inverter. The W/L-ratio of the enhancement-type transistor is almost the same as that of the switching transistor of the output inverter. The gates of the switching transistors are connected to one another. The load transistors are of the depletion type while the switching transistors are of the enhancement type. An embodiment is disclosed employing the above circuit and an additional pre-inverter circuit arrangement operating on a two-phase ratio technique controlled by a two-phase clock signal to match capacitances greater than that matched by the above circuit.