Address generator for generating addresses to read out data from a memory along angularly disposed parallel lines
US4477802A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1981 |
| Grant date | Oct 16, 1984 |
| Priority date | — |
| Expiry date | Dec 17, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0492
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An address generator responsible to input parameters for generating addresses to read out the content of a memory along parallel lines disposed at an angle to the orthogonal rows and columns of storage elements. The address generator has a first pair of registers coupled by an adder to generate line corrected X addresses, a second pair of registers coupled by an adder for generating first address corrections, an adder summing said line corrected X addresses with said first address corrections to generate X addresses, a third pair of registers coupled by an adder to generate line corrected Y addresses, a fourth pair of registers coupled by an adder to generate second address corrections, and an adder summing said line corrected Y addresses with said second address corrections to generate Y addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.