Matrix addressing of display devices
US4477805A · kind A · utility
9Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1981 |
| Grant date | Oct 16, 1984 |
| Priority date | — |
| Expiry date | Jun 4, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2203/02
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In a matrix array liquid crystal display on silicon with an a.c. drive involving periodic reversal of the potential of the counter-electrode this reversal is liable to produce a significant r.m.s. error voltage at each reversal. The OFF element error voltage is effectively eliminated by blanking all picture elements at the commencement of each reversal, and the ON error voltage more evenly shared by making this reversal occur after a non-integral number of frame scans.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.