Electrically programmable and erasable memory cell

US4477825A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Giora Yaron · Cupertino, US
• Ying K. Shum · Cupertino, US
• Ury Priel · Cupertino, US
• Jayasimha Prasad · San Jose, US
• Mark S. Ebel · Santa Clara, US

Key dates

• Filing date: Dec 28, 1981
• Grant date: Oct 16, 1984
• Expiry date: Dec 28, 2001

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/683

Abstract

An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.