Quadruply time-multiplex information bus
US4479178A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1981 |
| Grant date | Oct 23, 1984 |
| Priority date | — |
| Expiry date | Jul 2, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quadruply time-multiplexed bus for digital processor systems. The quadruply time-multiplexed information bus is interfaced to a processor and an external memory to transfer addresses, data and program instructions between the processor and the external memory. The interface at the external memory includes the capability to store the addresses of extended bus or instructions being accessed. These stored addresses may be modified from the processor by the processor transmitting new addresses over the information bus or by having the processor activate selected control signals in the information bus interface which causes the stored address to be modified in response to the control signals. This feature is useful to read a new instruction from external memory without the requirement of a new transmission of program instruction address every time a new instruction is fetched by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.