Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
US4479179A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1981 |
| Grant date | Oct 23, 1984 |
| Priority date | — |
| Expiry date | Oct 13, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access (DMA) unit either or both of which can be used to control the transfer of data between the I/O controller storage unit and the host processor. Typically, the DMA unit is used for cycle stealing data between the controller storage unit and the host processor. The cycle steal mechanism of the present invention enables the host processor to also initiate and control the cycle stealing of data to or from the controller storage unit without interrupting the program running in the controller microprocessor and without interrupting the cycle stealing operations of the DMA unit. This new cycle steal mechanism is the reverse of the normal situation where it is the microprocessor or DMA unit that is controlling the cycle stealing. This new cycle steal mechanism makes use of the microprocessor address set-up pulse (ALE) and the DMA unit address set-up pulse (ADSTB) to cause the cycle stealing of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.