System for updating error map of fault tolerant memory
US4479214A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 1982 |
| Grant date | Oct 23, 1984 |
| Priority date | — |
| Expiry date | Jun 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An online system is disclosed for mapping errors into an error map as data is transferred between a CPU and a relatively large fault tolerant semiconductor memory system without interfering with the normal use of the memory. The error mapping system permits a fault alignment exclusion mechanism to develop permute vectors which realign pair faults that were located at the same memory address. Having an up-to-date fault map which reflects the current error status of the memory when it is online and which reflects errors based on user data patterns greatly enhances the memory system and facilitates fault alignment exclusion efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.