Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment
US4479831A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1983 |
| Grant date | Oct 30, 1984 |
| Priority date | — |
| Expiry date | Jun 15, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the disclosed method, a transistor is fabricated by depositing an unpatterned layer of silicon on an insulating layer over a surface of a semiconductor substrate, with the silicon layer being deposited in an amorphous state to improve its uniformity in thickness and smoothness. Subsequently, while the silicon layer is still in the amorphous state, it is patterned by removing selected portions to form a gate. This patterning in the amorphous state improves the gates edge definition. Thereafter, the patterned amorphous silicon layer is heated to change it to polycrystalline silicon, thereby increasing its stability and conductivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.