Buffer inverter circuit with adaptive bias
US4481481A · kind A · utility
6Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1983 |
| Grant date | Nov 6, 1984 |
| Priority date | — |
| Expiry date | Feb 11, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/302
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit buffer inverter is created by cascading an emitter follower stage with a common emitter stage. Both stages include constant collector current loads. The emitter follower stage is adaptively biased from a current mirror that is driven from the collector of the emitter follower for the purpose of maximizing bipolar drive to the common emitter stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.