High speed data bus system
US4481625A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1981 |
| Grant date | Nov 6, 1984 |
| Priority date | — |
| Expiry date | Oct 21, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise one BIQ or more than one BIQ (a "BIQ" is a bus information quantum which is placed on the bus for one bus cycle). To implement the indivisibility of multiple-BIQ transfers, the control logic for each port includes screening circuitry responsive to the state of the port's input buffers, and further responsive to flags from the functional unit for selectively accepting or rejecting BIQ's, and further includes screening constraint circuitry to ensure that the port accepts all or none of the BIQ's that make up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers (for example, operations).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.