Online realignment of memory faults
US4483001A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 1982 |
| Grant date | Nov 13, 1984 |
| Priority date | — |
| Expiry date | Jun 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for operating a fault tolerant memory system which is provided with a fault alignment exclusion mechanism of the type disclosed in copending application Ser. No. 388,834. The method allows the assignment of a new permute vector to the fault alignment mechanism even though the memory is operating and storing user data. The method rearranges the data in the affected column by transferring data in one chip to another chip in the column through a buffer under the control of the old and new permute vectors. The transfer operation involves transferring the data at the same bit position from each chip in the column to a buffer under the control of the old permute vector and then transferring the data from the buffer to the same bit positions in other chips in the column determined by the new permute vector. The memory is then returned to the user for normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.