CMOS latch cell including five transistors, and static flip-flops employing the cell
US4484087A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1983 |
| Grant date | Nov 20, 1984 |
| Priority date | — |
| Expiry date | Mar 23, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node. A cross-coupled switching element comprising a second P-channel IGFET has its gate connected to the complementary data output node and is arranged to selectively connect the data storage node to the voltage supply node. A third P-channel IGFET has its channel arranged to selectively connect the data storage node to the voltage su…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.