Multiprocessor system
US4484275A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1983 |
| Grant date | Nov 20, 1984 |
| Priority date | — |
| Expiry date | Jun 17, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/173
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller. The bit can be reset to prevent that device controller from transmitting spurious signals which could interfere with interrupt requests being transmitted to the channel by other device controllers so that a failed device controller can be effecti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.