Electronic postage meter having improved security and fault tolerance features
US4484307A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1982 |
| Grant date | Nov 20, 1984 |
| Priority date | — |
| Expiry date | Feb 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00346
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A microcomputerized postage meter that provides high degrees of security and fault tolerance. The meter maintains data security under low power conditions by the use of functionally nonvolatile memory units. Register and other data which must survive normal and abnormal losses of power to the meter electronics are stored in dual redundant battery augmented memories (hereinafter designated BAMs). Upon detecting an error condition, the microcomputer writes an appropriate fault code to the BAMs. A mechanism for disabling the meter includes dual redundant flip-flops which are set to a "faulted" state upon detection by the microcomputer of a failure condition. These flip-flops are powered by the BAM batteries. They cannot be reset except by physical access to the meter interior, which access is only available to authorized personnel at the factory. The fault flip-flops are also set when the microcomputer fails to properly execute its own operating program. Once the meter has been set to a "faulted" state, the fault flip-flops hold two signals, MPCLR ans SYSCLR, true. The BAM contents may still be read out independently of the microcomputer which is prevented from accessing the BAMs. Thi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.