Etching method
US4484978A · kind A · utility
40Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1983 |
| Grant date | Nov 27, 1984 |
| Priority date | — |
| Expiry date | Sep 23, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to techniques for etching layered materials to produce features with beveled edges, for example, wells in silicon oxide layers employed in integrated circuit fabrication. An anisotropic etch may be employed to form wells with vertical walls in the silicon oxide layer, and an isotropic etch may be employed to bevel peripheral corners of the walls. In preferred embodiments, a double mask of a photoresist layer on an underlying thin film may be used to define the limits of the anisotropic and isotropic etches, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.