Monolithic CMOS low power digital level shifter
US4486670A · kind A · utility
73Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1982 |
| Grant date | Dec 4, 1984 |
| Priority date | — |
| Expiry date | Jan 19, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS digital level shifter circuit is provided which latches one transistor of a complementary transistor pair off when the other transistor of the pair is on to prevent direct current dissipation of power when the input signals to the shifter circuit are not in transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.