Circuit arrangement for extended addressing of a microprocessor system
US4486825A · kind A · utility
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3References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 15, 1981 |
| Grant date | Dec 4, 1984 |
| Priority date | — |
| Expiry date | Sep 15, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system including a microprocessor as the central processor unit and having memory read and memory write control outputs and peripheral device read and peripheral device write control outputs. The system also includes a peripheral device and a memory connected to the microprocessor via data-, address- and control buses and provided with read and write control inputs. The system employs combinational logic circuits for controlling the interconnections of the various system devices with the microprocessor in a predetermined way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.