Sensing and logic for multiple bit per cell ROM
US4488065A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1982 |
| Grant date | Dec 11, 1984 |
| Priority date | — |
| Expiry date | Aug 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5645
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit for determining the amplitude of an unknown impedance by comparing the voltage levels generated in a succession of current mirror circuits. In one form, the present circuit is connected to a ROM array comprised of FET devices having the potential of 2.sup.n different channel structures, impedances, to represent n different bits of data. When addressed, the selected ROM FET is coupled to a current mirror reference FET, whose commonly connected gate and drain electrodes are further coupled to a succession of 2.sup.n -1 current mirror FETs. Each of the current mirror FETs is connected in conductive series with an incrementally different impedance, the value of each impedance lying substantially midway between the 2.sup.n potential impedances possible in the ROM cell FET. The voltages on the current mirror FETs are individually compared to the voltage on the current mirror reference FET to generate a digital format representation of the relative magnitudes. The n data bits in the addressed ROM cell are then decoded by digital logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.