Multilayer metal silicide interconnections for integrated circuits
US4488166A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 1983 |
| Grant date | Dec 11, 1984 |
| Priority date | — |
| Expiry date | Apr 11, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76889
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.