Programmed logic array with external signals introduced between its AND plane and its OR plane
US4488230A · kind A · utility
22Cited by
9References
3Claims
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Key dates
| Filing date | Jun 20, 1983 |
| Grant date | Dec 11, 1984 |
| Priority date | — |
| Expiry date | Jun 20, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A combinational logic device, such as an AND gate, is connected to control the flow of information along a wordline from the AND plane to the OR plane of a PLA (programmed logic array). To each such combinational logic device is applied an input signal from a source external to the PLA, so that the PLA's output can respond relatively quickly to this input signal--that is, the PLA is capable of relatively quick decision making.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.