Fail-safe circuit for a microcomputer based system
US4488303A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1982 |
| Grant date | Dec 11, 1984 |
| Priority date | — |
| Expiry date | May 17, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fail-safe protection circuit for a data processor controlled system having a data bus for carrying data and comprising first logic for checking the operation of the data processor controlled system at periodic intervals not greater than T.sub.1 and for producing a trigger pulse at each check if the data processor is operating properly, second logic for detecting the absence of trigger pulses for a time period T.sub.2 to produce a control signal. Gating logic is responsive to the control signal to prevent the transmission of data through the data bus and a control circuit is also responsive to the control signal to reset the system to a predetermined operating state. The first logic responds to the resetting of the system to again produce the periodic trigger pulses if the system is operating properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.