Merged-transistor switch with extra P-type region
US4489341A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1982 |
| Grant date | Dec 18, 1984 |
| Priority date | — |
| Expiry date | Sep 27, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/406
Abstract
In one N-type epitaxial pocket of an integrated circuit there is formed a vertical NPN transistor and two other P-type regions each positioned adjacent but spaced from the P-type base region of the NPN. A metal gate over the gap between the base and one of the other P-type regions forms a high input-impedance P-MOS stage driving the NPN. A metal layer contacts both the NPN emitter and the PNP emitter formed by the third P-type region. This PNP transistor clamps the NPN collector-emitter to a safe voltage when switching an inductive load, and in a particularly efficient manner. A second P-MOS transistor is formed by extending the metal layer over the gap between the NPN-base and the third P-type region which transistor is capable of preventing leakage current out of the input P-MOS transistor in the off state form turning on the NPN transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.