Patent · US Expired

MOSFET Integrated delay circuit for digital signals and its use in color-televison receivers

US4489342A · kind A · utility

19Cited by
3References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 16, 1982
Grant dateDec 18, 1984
Priority date
Expiry dateFeb 16, 2002

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K2005/00195
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

To adjust time delays in equidistant steps, an inverter chain is provided with an even number of static inverters of identical topology. The output of one of the even-numbered inverters is connected to the signal output via a selector switch. During suitable frequency-measuring periods, an odd number of inverters is connected to form a ring by directly coupling the output of an odd-numbered inverter to the input of the first, and a digital measuring arrangement determines the time delay of the ring-connected portion from the frequency of the ring's self-excited oscillation. The output signal of the measuring arrangement is used to adjust the time delay of the inverter chain.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.