Hierarchical memories having two ports at each subordinate memory level
US4489381A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1982 |
| Grant date | Dec 18, 1984 |
| Priority date | — |
| Expiry date | Aug 6, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical memory system is disclosed comprising at least one dual-ported memory level, each port having access to a separate bidirectional data bus. The port facing the higher memory levels is equipped with a pair of data buffers having a bit width equal to the bit width of a single row of cells in the storage array contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The outer buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.