Information processor
US4489395A · kind A · utility
14Cited by
15References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 1982 |
| Grant date | Dec 18, 1984 |
| Priority date | — |
| Expiry date | May 6, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an information processor provided with a main memory device capable of simultaneously reading or writing 2N bit data. 2N bit data read out from the main memory device is applied to a selector through a memory bus of 2N-bit construction. The selector devides the data comprising 2N bits in two N-bit units and then outputs that data into a scratch pad memory device constituted by N bits X M addresses. The data written in the scratch pad memory device in N bit units is processed by a central processing unit of N-bit architecture. For accessing the operand, the information processor accesses the main memory in N-bit units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.