Arithmetic device for concurrently summing two series of products from two sets of operands
US4490807A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1983 |
| Grant date | Dec 25, 1984 |
| Priority date | — |
| Expiry date | Dec 1, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.