Multi-device apparatus synchronized to the slowest device
US4493053A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1982 |
| Grant date | Jan 8, 1985 |
| Priority date | — |
| Expiry date | Dec 10, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous apparatus synchronized to the operation of the slowest device is disclosed, comprising a plurality of devices such as first-in first-out buffer memories (FIFOs) connected to at least one synchronizing mechanism such as a full adder circuit. Each device generates a signal to indicating readiness to operate and a signal indicating completion of operation. Each device receives a signal causing the device to operate and a signal causing the device to stop operating. The synchronizing mechanism generates the operate signal upon sensing the readiness signals of all the devices and continues to generate the operate signal while at least one of the ready signals is sensed. The synchronizing mechanism generates the stop signal upon sensing the completion signal from all of the devices and continues to generate that signal while at least one of the completion signals is sensed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.