Scan testable integrated circuit
US4493077A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1982 |
| Grant date | Jan 8, 1985 |
| Priority date | — |
| Expiry date | Sep 9, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A large scale sequential integrated circuit is made amenable to scan design testing by the inclusion of special multiplexing and storage circuits which respond to a pair of test control pulses to reconfigure the circuit to include one or more shift registers and to step the scan test data through the shift registers. In particular, the pair of test control pulses are applied to the two terminals to which, in normal operation, are applied the clock pulses which are used to control the storage elements and which, in such operation, are never both simultaneously high. To initiate the scan test operation, these test control pulses are made simultaneously high and the circuitry responds to such conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.