High speed bus architecture
US4494192A · kind A · utility
100Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1982 |
| Grant date | Jan 15, 1985 |
| Priority date | — |
| Expiry date | Jul 21, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is shown and described a high speed bus architecture which uses a common control bus and permits high speed data transfer between a plurality of active and/or passive users while reducing the system overhead structure which was previously required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.