Frequency divider presettable to fractional divisors
US4494243A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1982 |
| Grant date | Jan 15, 1985 |
| Priority date | — |
| Expiry date | Nov 16, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle. For arbitrary fractional divisors, the maximum phase-jitter amplitude is equal to the smallest adjustable time delay and, hence, considerably smaller than the clock period (T') of the signal to be divi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.