Computer memory address matcher and process
US4495565A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1981 |
| Grant date | Jan 22, 1985 |
| Priority date | — |
| Expiry date | Nov 9, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address matcher and process for same used as an aid in debugging computer programs. Each of a plurality of random access memories (RAMs) is addressed by a different subfield of a computer memory address so that each access of the computer memory also causes a read of each of the RAMs. Each RAM is programmed with encoded data to define upper and lower block addresses for that subfield of the computer memory address with which it is associated. An output circuit decodes the encoded data read from each of the RAMs as a result of a computer memory access and generates a signal if the computer memory address lies within the monitored address block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.