Data processing system having synchronous bus wait/retry cycle
US4495571A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1982 |
| Grant date | Jan 22, 1985 |
| Priority date | — |
| Expiry date | Jan 15, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.