Multi-bit read only memory circuit
US4495602A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1981 |
| Grant date | Jan 22, 1985 |
| Priority date | — |
| Expiry date | Dec 28, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory circuit (10) includes an array of memory transistors including a row of such transistors (12-28) connected to a common word line (30). For each column of memory transistors there is provided a set of reference transistors which receive a word line signal which is concurrent with any word line signal provided to any word line in the memory array. Column decode signals (CD1-CD4) are provided to select a memory transistor on an activated word line and to select corresponding reference transistors. The memory transistor is fabricated to have one of a plurality of threshold voltages. The reference transistors are fabricated to have different predetermined threshold voltages. The drive signals are applied through the word lines concurrently to the selected memory transistor and corresponding reference transistors to cause the transistors to transition from a first state to a second state. Decoding circuitry is provided to determine the time sequence of transition of the memory transistor relative to the reference transistors. This decoding produces an output signal which corresponds to the threshold voltage and therefore the data state for the selected memory transisto…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.