Test system for segmented memory
US4495603A · kind A · utility
26Cited by
5References
28Claims
0Family size
Inventor
Key dates
| Filing date | Jul 31, 1980 |
| Grant date | Jan 22, 1985 |
| Priority date | — |
| Expiry date | Jul 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory system is organized into a plurality of segments and is equipped with multiplexed or multifunctional pin for input/output purposes; e.g. the memory address pins, since there is a portion of each memory cycle during which the logic state of the address pins is unimportant. Logic means is provided for coupling the multiplexed pins to the memory segments through the input/output lines upon the occurrence of a test clock signal. The test clock signal is generated during the don't-care portion of the memory cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.