Low power clock generator
US4496852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1982 |
| Grant date | Jan 29, 1985 |
| Priority date | — |
| Expiry date | Nov 15, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit for producing with very little power dissipation an output clock signal having levels determined by positive and negative power supply levels from an input clock signal having levels determined by the positive power supply level and ground. In a low state of the input clock signal, an upper or first transistor of an output transistor pair connected in series between positive and negative power supply levels is turned off by applying a ground level to the base thereof, while the lower or second transistor of the output transistor pair is turned off by applying a positive potential to its base. When the input clock signal makes a transition from the low state to the high state, a bootstrap capacitor is charged between the positive and negative power supply levels to provide a boosted positive voltage to turn on the upper transistor. While the bootstrap capacitor is charging, the base of the lower transistor is lightly grounded to partially turn it on. When the charge on the bootstrap capacitor has reached a predetermined level, the base of the first transistor is taken to the negative power supply level through an inverting transistor, the base of which also…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.