Stacked interdigitated lead frame assembly
US4496965A · kind A · utility
51Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1984 |
| Grant date | Jan 29, 1985 |
| Priority date | — |
| Expiry date | Jan 9, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package having a large number of external connections is assembled using two lead frames stacked one atop the other. The lead frames have complementary lead patterns which interdigitate to provide a very close lead spacing at the periphery of a semiconductor chip on which a complex integrated circuit is fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.