Method of generating time delay
US4497035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1982 |
| Grant date | Jan 29, 1985 |
| Priority date | — |
| Expiry date | Jan 5, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to deliver an input signal of each operation cycle after a desired time delay, there are disposed data memory means for storing the input signal, counter means for appointing write addresses of the data memory means, and address memory means for appointing read addresses of the data memory means. The address memory means is divided into partial memory areas equal in number to time delay elements, whereupon while sampling the input signal at a predetermined sampling period and changing the count value of the counter means one by one for each of the desired time delay elements at each sampling point, the variations of the input signal in a sampling interval between the particular sampling point and the adjacent sampling point are successively written into the memory means. Further, while changing the contents of the partial memory areas corresponding to the desired time delay element to the number of the time delay elements in each sampling interval, the variations in a sampling interval preceding a predetermined sampling number to the particular sampling interval are successively read out from the memory means. The input signal of each operation cycle in the preceding sampl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.