Self-clocking binary receiver
US4497060A · kind A · utility
53Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1982 |
| Grant date | Jan 29, 1985 |
| Priority date | — |
| Expiry date | Dec 8, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Binary data is transmitted as signals of two different pulsewidths to respectively represent logic "0" and "1". At the data receiver, the ratio of the pulsewidths is converted into a corresponding voltage ratio, which, in turn, is applied through a voltage divider to develop clock- and data-control signals at two different levels. Switching devices are respectively actuated whenever the clock- and data-control signals reach preset voltage levels to respectively produce self-synchronized clock and data pulses corresponding to the received binary data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.