Segregator functional plane for use in a modular array processor
US4498134A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1982 |
| Grant date | Feb 5, 1985 |
| Priority date | — |
| Expiry date | Jan 26, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Segregator Functional Plane capable of dynamically segregating any number, or subset, of a Modular Array Processor's functional planes, either in terms of control or data exchange, or both, from the remainder. This is provided by interspersing a number of Segregator Functional Planes throughout the Array Processor so that a Segregator Functional Plane is architecturally located between each of the adjacent subsets of the Array Processor's functional planes. The Segregator Functional Plane nominally includes an array of pseudomodules that corresponds to the module arrays of the other functional planes of the Array Processor so that a pseudo-module is architecturally present between correspondingly adjacent modules of each Elemental Processor. These pseudo-modules are comprised of switches that may be commonly activated to functionally sever their respective Elemental Processor data bus lines. The Segregator Functional Plane also includes a second set of commonly activatable switches for functionally severing each of the Address Bus, Control Bus, Clock, Address Valid, and Configuration Latch Reset lines. Further, a third set of commonly activatable switches are included within the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.