Multiplexer and demultiplexer circuits for analog signals
US4498166A · kind A · utility
Inventor
Key dates
| Filing date | Nov 12, 1982 |
| Grant date | Feb 5, 1985 |
| Priority date | — |
| Expiry date | Nov 12, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J7/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
There is disclosed a multiplex system for combining a plurality of analog or other type input signals at a transmitter site to provide a composite signal for transmission to a receiver site via a common transmission channel. At the transmitter, a reference ramp signal is generated and then peak detected to provide a plurality of proportional threshold level signals, each one associated with one input signal. These threshold signals are employed as inputs to comparators which also receive an input signal with one comparator for each input signal or channel. The outputs of the comparators are summed to provide a staircase composite signal for transmission to the receiver site. At the receiver, the staircase signal is peak detected to again provide a series of proportional threshold levels each of which is applied to a separate comparator at one input. Another input of the comparator receives the staircase signal to provide at the output a replica of the original input signal. There is no separate synchronization required by the transmitter and the receiver according to the system operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.