Parallel cyclic redundancy checking circuit
US4498174A · kind A · utility
22Cited by
1References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1982 |
| Grant date | Feb 5, 1985 |
| Priority date | — |
| Expiry date | Aug 25, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1813
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A parallel cyclic redundancy checking circuit which determines the validity of digital, binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers are used to store sequentially occurring parallel groups of data and a feedback network comprising exclusive-or gates provide a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.