Printed circuit board defect detection of detecting maximum line width violations
US4500202A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 1983 |
| Grant date | Feb 19, 1985 |
| Priority date | — |
| Expiry date | Aug 8, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automatic printed wiring (or circuit) board (PWB) method for detecting maximum line width violations is described. The method utilizes an array of optical sensors for optically inspecting a printed wire circuit. The array forms a binary image pattern of the PWB which is tested for compliance with logical rules of correctly printed PWB's regarding maximum line width. The detector comprises a plurality of CCD arrays arranged to form a series of pixels consisting of electronic binary signals corresponding to the instantaneous image viewed by each element in the CCD array. These pixels are formed in an image data stream of sequential pixels line-by-line of the CCD array, i.e., pixel sequential line sequential digital image data. The digital pixel data is formatted in an "N" by "N" bit matrix of points in proper image orientation. All such points are available for sampling. Each pixel progressively occupies each point in the matrix in proper orientation to its neighbors. Each pixel passes through each "N" bit point of the matrix thus forming a moving "window" of "N" by "N" bits in size of a portion of the image viewed by the CCD array. The contents of the matrix are addressed and sel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.