Multilevel masterslice LSI with second metal level programming
US4500906A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1982 |
| Grant date | Feb 19, 1985 |
| Priority date | — |
| Expiry date | May 14, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising a semiconductor bulk in which a plurality of basic circuit elements are formed, first interconnecting lines being formed on a first insulation layer of said semiconductor bulk, a second insulation layer formed on both said first insulation layer and said first interconnecting lines, and a cell in which said basic circuit elements are connected with each other by said first interconnecting lines, wherein the first interconnecting line for connecting two of said basic elements in the cell has two separated parts, one end of each of said parts is connected to one of said basic elements, said second insulation layer is provided with a pair of through-holes in the cell, and each of said pair of through-holes contacts with the other end of each of said parts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.