Page mode memory system
US4500961A · kind A · utility
7Cited by
6References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 3, 1983 |
| Grant date | Feb 19, 1985 |
| Priority date | — |
| Expiry date | Jun 3, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-page ROM uses programmable pointers for selection of a page. The pointers each have a preliminary latch circuit, an output latch circuit, and a delay circuit. The preliminary latch circuit receives and stores program address signals when a first signal is present. The output latch receives the address stored in the preliminary latch when a second signal is present. The delay circuit removes the first signal before the second signal is present and delays the presence of the first signal for a delay period following the removal of the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.